{"product_id":"dsmb144-57360001-el-abb-memory-module-advant-master-s100-series","title":"DSMB144 57360001-EL ABB Memory Module Advant Master S100 Series","description":"\u003cp\u003eConfigured for non-volatile firmware and user-program image retention in ABB Advant Master S100 controller racks, the \u003cstrong\u003eABB DSMB144 57360001-EL\u003c\/strong\u003e (\u003cstrong\u003eDSMB144\u003c\/strong\u003e Memory Module) presents a 512 KB EPROM array to the PM510\/PM630 or AC410\/AC450 CPU across the 32-bit S100 backplane and CEX bus bridge.\u003c\/p\u003e\n\u003ch3\u003ePart Number and Sibling Variant Map\u003c\/h3\u003e\n\u003cp\u003eDSMB144 is the base type; 57360001-EL is the ABB order number, EXC57360001-EL the exchange refurb loop ID. The \"-EL\" suffix is not a hardware revision, it is the country\/batch code for Sweden-origin boards. Do not cross-swap with DSMB114 (57360001-MG), DSMB116 (57360001-EB), DSMB127 (57360001-HG, battery RWM), or DSMB175 (57360001-KG) — same Eurocard edge, different decode PAL and socket count. The board ships as an empty 16-socket carrier; PROMs are not fitted.\u003c\/p\u003e\n\u003ch3\u003eHardware Specifications\u003c\/h3\u003e\n\u003cfigure class=\"table\"\u003e\n\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003eParameter\u003c\/th\u003e\n\u003cth\u003eSpecification\u003c\/th\u003e\n\u003c\/tr\u003e\n\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003eModel\u003c\/td\u003e\n\u003ctd\u003eDSMB144 57360001-EL\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eBrand\u003c\/td\u003e\n\u003ctd\u003eABB\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOrigin\u003c\/td\u003e\n\u003ctd\u003eSweden\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eWeight\u003c\/td\u003e\n\u003ctd\u003e0.32 kg (bare board, no PROMs)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eShipping Dimensions\u003c\/td\u003e\n\u003ctd\u003e255 mm x 235 mm x 10 mm\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOperating Temp\u003c\/td\u003e\n\u003ctd\u003e0 deg C to +60 deg C (some batches -20 deg C lower bound)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eStorage Temp\u003c\/td\u003e\n\u003ctd\u003e-40 deg C to +85 deg C\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMedia\u003c\/td\u003e\n\u003ctd\u003e16 x 32-pin UV-EPROM sockets, 32 KB each, 512 KB total\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSupported PROM\u003c\/td\u003e\n\u003ctd\u003e4911004-128 (32 KB UV EPROM, equiv 27C256)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eWrite Method\u003c\/td\u003e\n\u003ctd\u003eOff-board UV erase (15-20 min) + programmer burn; no in-situ write\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eBackplane Power\u003c\/td\u003e\n\u003ctd\u003e5 VDC from S100 CPU rack\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePower Consumption\u003c\/td\u003e\n\u003ctd\u003e3.8 W max (all sockets populated and addressed)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eBus Interface\u003c\/td\u003e\n\u003ctd\u003eS100 32-bit parallel + CEX bus tap to PM-class CPU\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eIsolation\u003c\/td\u003e\n\u003ctd\u003eOpto-decoupled bus buffers, 1500 VDC\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eIndicators\u003c\/td\u003e\n\u003ctd\u003ePWR, MEM, BUS, ERR LEDs\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMounting\u003c\/td\u003e\n\u003ctd\u003eS100 controller companion memory slot (1 SU), not I\/O slot\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eCompliance\u003c\/td\u003e\n\u003ctd\u003eCE, IEC 61000-4, RoHS exempt 2011\/65\/EU Art 2(4)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eTariff Code\u003c\/td\u003e\n\u003ctd\u003e8523510000\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003c\/figure\u003e\n\u003ch3\u003eS100 Backplane Decode and EPROM Image Behavior\u003c\/h3\u003e\n\u003cp\u003eDSMB144 sits immediately right of the PM510\/PM511\/PM630 CPU or under the AC410\/AC450 CPU daughter site. On 5 VDC power-up the CPU asserts chip-select lines mapped to the 16-socket 32 KB window; the first socket (U1) typically holds the boot strap, subsequent sockets hold firmware segments, PID\/sequence libraries, and user control logic in contiguous or banked pages depending on the MasterTool build. Because the media is UV-EPROM, there is no electrical erase in rack — runtime writes from Advant Control Builder go to CPU RAM or DSMB127 RWM, never to DSMB144. Backplane bus communication velocity is static-decoded; the module exerts no handshake latency. Hot-swap is not permitted: S100 I\/O cards allow live swap, DSMB144 does not — extracting under 5 VDC arcs the edge connector and can latch the CPU bus interface. Redundancy is handled at CPU level (AC450 dual CPU), not by mirroring two DSMB144 images live; the standby CPU holds its own DSMB144.\u003c\/p\u003e\n\u003ch3\u003eOrdering Info\u003c\/h3\u003e\n\u003cul\u003e\n\u003cli\u003e1 x DSMB144 bare PCB 57360001-EL, 16 EPROM sockets empty\u003c\/li\u003e\n\u003cli\u003e0 x 4911004-128 PROMs fitted (ordered separately)\u003c\/li\u003e\n\u003cli\u003e1 x RoHS exemption sticker (Art 2(4))\u003c\/li\u003e\n\u003cli\u003e2 x Eurocard ejector clips pre-fitted\u003c\/li\u003e\n\u003cli\u003eNo screws, no ribbon, no UV window covers supplied\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch3\u003eSlot Fitting and PROM Burn Rule\u003c\/h3\u003e\n\u003cul\u003e\n\u003cli\u003eInsert only into the CPU companion memory slot marked \"MEM\" on the S100 controller rack, never into DSAI\/DSDI\/DSAO I\/O bays.\u003c\/li\u003e\n\u003cli\u003eSeat each 4911004-128 with notch to pin 1; reversed PROM burns the socket decode PAL on first access.\u003c\/li\u003e\n\u003cli\u003eKeep EPROM UV windows covered until after commissioning; shop fluorescent exposure beyond 5 min causes bit drift in unprogrammed cells.\u003c\/li\u003e\n\u003cli\u003eFull eject both levers before pull; partial seat leaves MEM LED dark and CPU halts at POST 0xMEM.\u003c\/li\u003e\n\u003cli\u003eSingle-point bond S100 5 VDC logic ground to 24 VDC field ground at rack frame, do not daisy ground through DSMB144 buffers.\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch3\u003eFrequently Asked Questions\u003c\/h3\u003e\n\u003cp\u003eDoes DSMB144 store retentive process variables?\u003c\/p\u003e\n\u003cp\u003eNo. UV-EPROM is code-only, non-volatile, no battery. Retentive tags and setpoints live on DSMB127 battery-backed RWM or CPU internal RAM with supercap. Swapping DSMB144 never alters held values but loses the executable image if PROMs are not re-burned.\u003c\/p\u003e\n\u003cp\u003eCan Control Builder download logic directly to DSMB144?\u003c\/p\u003e\n\u003cp\u003eNo. EPROM cannot be electrically written in situ. Project changes require pulling 4911004-128, UV erasing 15-20 min, burning on a 27C256 programmer, re-seating. Online download targets CPU RAM or flash card, not this board.\u003c\/p\u003e\n\u003cp\u003eWhat POST result appears with empty sockets?\u003c\/p\u003e\n\u003cp\u003eCPU halts at memory check, ERR LED on DSMB144 lit, AC450 shows 0xMEM stop code. Partial population is allowed only if the MasterTool image map is explicitly shortened and PROM count matches the chip-select range.\u003c\/p\u003e\n\u003cp\u003eIs live swap possible on running AC450?\u003c\/p\u003e\n\u003cp\u003eNo. Unlike S100 I\/O cards which support hot insertion in 10 s, DSMB144 is on the CPU local bus. Extracting under 5 VDC backplane power arcs the edge gold fingers and can destroy the CPU bus transceiver. Stop CPU, drop 5 VDC rail, then extract.\u003c\/p\u003e\n\u003cp\u003eWhy does a new board not boot the controller?\u003c\/p\u003e\n\u003cp\u003e57360001-EL ships as bare carrier, 16 empty sockets. No PROM, no image. You must burn the AC410\/AC450 firmware set plus user project PROMs offline. A bare board yields continuous ERR blink, not a partial boot.\u003c\/p\u003e\n\u003cp\u003eWhich PROM fits the 16 sockets?\u003c\/p\u003e\n\u003cp\u003e32 KB UV-EPROM, ABB 4911004-128 (industry 27C256). 64 KB or 128 KB dies physically fit but decode stops at A14; upper half ignored. Mixing 16 KB dies forces bank misalignment and checksum fail.\u003c\/p\u003e\n\u003cp\u003eCan DSMB144 replace DSMB127 in same slot?\u003c\/p\u003e\n\u003cp\u003eMechanically yes, electrically no. DSMB127 adds lithium-backed RWM for retentive data and smaller EPROM count. Substituting 144 for 127 forces full project reburn into EPROM and loses all battery-held variables unless migrated to CPU RWM first.\u003c\/p\u003e\n\u003cp\u003eWhat is the 5 VDC backplane draw?\u003c\/p\u003e\n\u003cp\u003eTypical 760 mA (3.8 W) with all 16 sockets populated and selected. Empty board draws ~210 mA for LED and buffer quiescence. This loads the DSSR122 5 VDC 40 A rail shared with PM630 and CEX bridge; keep CPU slot group under budget.\u003c\/p\u003e","brand":"ABB","offers":[{"title":"Default Title","offer_id":46021160861869,"sku":"57360001-EL","price":88.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0733\/1613\/9181\/files\/57360001-EL_36.jpg?v=1784537332","url":"https:\/\/www.maxwellplc.com\/products\/dsmb144-57360001-el-abb-memory-module-advant-master-s100-series","provider":"Maxwell PLC Ltd","version":"1.0","type":"link"}