Configured for analog signal processing in CP1 series programmable logic controllers, the Omron CP1W-MAB221 (CP1W-MAB221 Analog I/O Option Board) provides direct physical/electrical execution.

Technical Identifier Matrix

• Primary Part Number: CP1W-MAB221
• Base Model Family: CP1W Option Board Series
• Hardware Type: Analog Input/Output Expansion Board
• Host CPU Compatibility: CP1H, CP1L, CP1E (CP1E-N30/40/60 or NA20 CPU units)
• Mounting Slot Placement: CPU Unit Option Board Slot 1 or Slot 2 (CPU model dependent)

Hardware Specifications

Omron PLC Backplane Bus & Signal Processing

The CP1W-MAB221 interfaces directly with the CPU internal bus using low-latency parallel interconnects. Signal conversion is executed via internal multiplexing and high-speed A/D-D/A converters without requiring external power supplies for board logic operation. Dedicated memory addresses within the PLC CIO board allocation map the analog values directly into data registers, optimizing execution velocity across cyclic scan sequences. The board hardware handles physical channel isolation from internal CPU logic to prevent stray noise coupling into the main processing unit.

Package Contents & Ordering Information

• 1x Omron CP1W-MAB221 Analog I/O Option Board
• 1x Set of CPU mounting locking screws
• 1x Field wiring pin terminal connector assembly
• 1x Instruction manual sheet

Field Installation Guidelines

• Board Installation: Power down the CPU unit complete system supply. Remove the target Option Board slot cover on the front panel of the CP1 CPU. Insert the CP1W-MAB221 unit straight into the board connector until fully seated, and secure the board using the provided hardware.
• Wiring Practice: Use twisted-pair shielded cable for all analog input and output circuits. Separate field analog lines from high-voltage AC lines and inductive motor cables by a minimum distance of 200 mm.
• Shield Grounding: Connect cable shielding to the functional ground (FG) terminal on the PLC CPU end only. Leave the sensor/actuator side ungrounded to prevent ground loop circulating currents.
• Current Mode Input: Set the input selection dip switches on the rear side of the option board prior to mounting into the CPU slot (Select ON for 0-20 mA mode, OFF for 0-10 VDC mode).

Frequently Asked Questions

• Is hot-swapping permitted for the CP1W-MAB221 board while the PLC is powered?

  No. Inserting or removing the option board while the CPU unit is energized will cause hardware damage to the backplane interface and fault the main processor.

• What signal ranges are supported on the analog channels?

  Inputs and outputs support 0-10 VDC voltage ranges or 0-20 mA current ranges configurable per channel via hardware dip switches and system setup memory registers.

• Does the option board require an external 24 VDC auxiliary power source?

  No. Operating power for the A/D and D/A conversion circuitry is drawn directly from the host CPU 5 VDC internal bus supply.

• What is the conversion resolution of the CP1W-MAB221 module?

  The digital resolution is 1/1200 full scale, yielding a mapped integer digital value ranging from 0 to 1200 (0000 to 04B0 Hex) in the CPU memory words.

• How are input and output words addressed in the PLC program?

  The CPU assigns specific fixed CIO memory addresses based on the slot index (Slot 1 or Slot 2) where the option board is installed in the CPU front panel.

• What wiring conductor sizes are supported by the push-in terminal block?

  The terminal block accepts solid or stranded wires with cross-sectional areas from 0.08 mm2 to 1.25 mm2 (AWG 28 to AWG 16) fitted with ferrules.

• What is the isolation rating between the analog channels?

  Channels share a common ground reference; there is no channel-to-channel galvanic isolation, but standard galvanic isolation exists between analog signals and CPU digital logic.

• How does cycle time impact the analog update frequency?

  Analog conversion timing depends on PLC scan cycle performance, with a minimum base conversion rate of 6.0 ms total for all active channels combined.