Configured for high-speed multi-axis motion and sequence execution in EtherCAT networks, the Omron NJ501-1500 (NJ501-1500 Motion Controller) provides direct physical/electrical execution. It delivers a primary task cycle time of 0.5 ms and manages up to 64 real and virtual motion axes. Equipped with 20 MB program memory, 6 MB variable memory, an EtherCAT Master port, an EtherNet/IP interface, and an OPC-UA server, the unit controls industrial machine processes while interfacing with CJ Series expansion I/O backplanes.

Model Identification & Configurator

• NJ: Sysmac NJ-Series Motion Control CPU Architecture.
• 5: 501 High-Performance Processing Tier.
• 01: Standard CPU Hardware Platform.
• 1500: Motion Control Profile Supporting 64 Axes with Built-In OPC-UA Protocol.

System Specifications

Deterministic Network & Firmware Mechanics

The CPU uses high-speed backplane communication velocity over the CJ I/O Bus to exchange field data while maintaining precise synchronization on EtherCAT master cycles. Built-in Profinet / EtherNet/IP deterministic networks isolate host enterprise monitoring from deterministic servo drive communication. The internal controller architecture uses firmware flash compatibility for Sysmac Studio updates, sustaining jitter-free execution across high I/O density scaling configurations without compromising the 0.5 ms primary task execution window.

Box Deliverables

• 1 x Omron NJ501-1500 Motion Controller Unit
• 1 x End Cover (CJ1W-TER01)
• 1 x Operation Terminal Battery

Installation & Wiring Rules

• Rack Mounting: Mount the CPU unit onto the left-most position of the CJ-series base rack, securing the side slider locking mechanism firmly.
• End Cover Attachment: Always attach the CJ1W-TER01 bus end cover to the right-most unit on the rack to properly terminate the CJ backplane bus.
• EtherCAT Cable Connection: Use Category 5e or higher STP (shielded twisted pair) cables for the EtherCAT Master port to prevent industrial noise interference.
• Earth Grounding: Wire the ground terminal (100 ohm or less dedicated ground) using a conductor size of at least 2 mm2 to reduce electrical noise.
• Battery Safety: Insert the included memory backup battery into its dedicated compartment prior to powering up the CPU for program retention.

Technical FAQ

• Can CJ I/O modules be hot-swapped on the NJ501-1500 backplane during execution?

  No. You must shut down power to the CPU rack before removing or adding CJ I/O modules to prevent backplane circuit corruption.

• How does the EtherCAT Master port handle synchronization with 64 motion axes?

  The controller utilizes distributed clock (DC) synchronization over EtherCAT, locking axis update cycles directly to the 0.5 ms primary task loop.

• What protocol is used to transmit data to SCADA or host MES systems directly?

  The CPU includes a native OPC-UA server integrated into its firmware, allowing secure client connections over the built-in EtherNet/IP network interface.

• What happens if the internal memory backup battery fails?

  The CPU triggers a battery low alarm, but non-volatile flash memory retains the user application program. Variable data in RAM may be lost upon power removal.

• Are additional axis licenses required to control all 64 axes on the NJ501-1500?

  No. The NJ501-1500 hardware natively supports control for up to 64 total axes (including synchronous and virtual axes) out of the box.

• Which programming tools are supported for configuring the CPU?

  The unit is fully configured, programmed, and debugged via Omron Sysmac Studio software using IEC 61131-3 compliant languages and motion function blocks.

• Does the USB port support continuous network routing to connected servo drives?

  Yes. The USB interface provides a direct engineering gateway for Sysmac Studio to route through the CPU onto the EtherCAT network for servo tuning.

• How is the CJ I/O expansion bus isolated from the CPU core logic?

  The internal CJ I/O bus interface uses optical galvanic isolation barriers to prevent field-side voltage transients from affecting the main CPU microprocessor.